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Si5018
SiPHYTM OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC
Features
Complete high-speed, low-power, CDR solution includes the following:
! !
Supports OC-48 /STM-16 & FEC ! Low power--270 mW (typ OC-48) ! ! Small footprint: 4x4 mm ! DSPLLTM Eliminates external ! loop filter components ! ! 3.3 V tolerant control inputs !
Exceeds all SONET/SDH jitter specifications Jitter generation 3.0 mUIrms (typ) Device powerdown Loss-of-lock indicator Single 2.5 V Supply Ordering Information: See page 17.
Applications
!
CLKOUT+
description
The Si5018 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/STM-16 data rates. In addition, support for 2.7 Gbps data streams is also provided for applications that employ forward error correction (FEC). DSPLLTM technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5018 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (-40 to 85 C).
REXT VDD GND REFCLK+ REFCLK- 1 2 3 4 5
20 19 18 17 16 15 PWRDN/CAL VDD DOUT+ DOUT- VDD
CLKOUT- 14 13 12 11 10 DIN-
SONET/SDH/ATM routers ! Add/drop multiplexers ! Digital cross connects ! SONET/SDH test equipment
!
Optical transceiver modules ! SONET/SDH regenerators ! Board level serial links
Pin Assignments Si5018
GND
GND 7 VDD
GND Pad Connection
6 LOL
GND 8 GND
9 DIN+
Functional Block Diagram
LOL
D IN + D IN -
2
BU F
D SPLLTM Phas e-Locked Loop
R etim er
BU F
2
D OU T + D OU T - PW R D N /C AL
Bias
2
BU F
2
C LKOU T + C LKOU T -
R EXT
R EF C LKIN + R EF C LKIN -
Rev. 1.2 1/04
Copyright (c) 2004 by Silicon Laboratories
Si5018-DS12
Si5018
2
Rev. 1.2
Si5018 TABLE O F CONTENTS
Section Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DSPLLTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outline: SI5018-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4x4 mm 20L MLP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.2
3
Si5018
Detailed Block Diagram
Retim e
DOUT+ DOUT-
c
DIN+ DIN-
Phase Detector
A/D
DSP n
VCO
CLK Divider
CLKOUT+
c
CLKOUT-
REFCLK+ REFCLK- Lock Detector LOL
REXT
Bias G eneration
Calibration
PWRDN/CAL
4
Rev. 1.2
Si5018
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Si5018 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 2.375 Typ 25 2.5 Max1 85 2.625 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. 2. The Si5018 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "Typical Application Schematic" on page 9.
V SIGNAL+ VICM,VOCM Differential I/Os SIGNAL- VIS Single-Ended Voltage
(SIGNAL+) - (SIGNAL-)
Differential Voltage Swing
VID,VOD (VID = 2VIS)
Differential Peak-to-Peak Voltage t
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t C-D DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
DOUT, CLKOUT tF tR
80% 20%
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.2
5
Si5018
Table 2. DC Characteristics
(VDD = 2.5 V 5%, TA = -40 to 85 C)
Parameter Supply Current Power Dissipation Common Mode Input Voltage (DIN, REFCLK)* Single Ended Input Voltage (DIN, REFCLK)* Differential Input Voltage Swing (DIN, REFCLK)* Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) OC48 Differential Output Voltage Swing (CLKOUT) OC48 Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Short to GND (DOUT,CLKOUT) Output Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current
Symbol IDD PD VICM VIS VID RIN VOD VOD VOCM ROUT ISC(-) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN
Test Condition
Min -- --
Typ 108 270 .80 x VDD -- -- 100 990 900 VDD - 0.23 100 25 -14.5 -- -- -- -- -- -- -- 25
Max 122 320 -- 750 1500 116 1260 1260 -- 116 31 -- .8 -- 10 10 0.4 -- -- 35
Unit mA mW V mVPP mVPP mVPP mVPP V mA mA V V A A V V k A
varies with VDD See Figure 1 See Figure 1 Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended
-- 200 200 84 780 550 -- 84 -- -17.5 -- 2.0 -- --
IO = 2 mA IO = 2 mA VPWRDN 0.8 V
-- 2.4 10 15
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min), and the unused input must be ac coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (DIN+, DIN-, REFCLK+, or REFCLK-) must not exceed the specified maximum Input Voltage Range (VIS max).
6
Rev. 1.2
Si5018
Table 3. AC Characteristics (Clock and Data)
(VA 2.5 V 5%, TA = -40 to 85 C)
Parameter Output Clock Rate Output Rise/Fall Time Clock to Data Delay FEC (2.7 GHz) OC-48 Input Return Loss
Symbol fCLK tR,tF tC-D
Test Condition
Min 2.4
Typ -- 80 250 250 16 13
Max 2.7 110 270 270 -- --
Unit GHz ps ps dB dB
Figure 3 Figure 2
-- 225 225
100 kHz-2.5 GHz 2.5 GHz-4.0 GHz
-- --
Table 4. AC Characteristics (PLL Characteristics)
(VA 2.5 V 5%, TA = -40 to 85 C)
Parameter Jitter Tolerance*
Symbol JTOL(P-P)
Test Condition f = 600 Hz f = 6000 Hz f = 100 kHz f = 1 MHz
Min 40 4 4 .4 -- -- -- --
Typ -- -- -- -- 2.9 25 -- 0.03 1.5 60 50 -- -- 600
Max -- -- -- -- 5.0 55 2.0 0.1 1.7 150 60 100 168.75 750
Unit UIPP UIPP UIPP UIPP mUI mUI MHz dB ms s % ppm MHz ppm
RMS Jitter Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth* Jitter Transfer Peaking*
JGEN(rms) JGEN(PP) JBW JP TAQ
with no jitter on serial data with no jitter on serial data
Acquisition Time
After falling edge of PWRDN/CAL From the return of valid data
1.45 40 40 -100 19.44
Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance Reference Clock Range Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock)
CDUTY CTOL
LOL
450
LOCK
150
300
450
ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 - 1 data pattern.
Rev. 1.2
7
Si5018
Table 5. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k) TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 2.8 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 1 Unit V V V mA C C kV
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Symbol JA Test Condition Still Air Value 38 Unit C/W
8
Rev. 1.2
Si5018
Typical Application Schematic
Powerdown Loss-of-Lock Indicator
High-Speed Serial Input System Reference Clock
DIN+ DIN- REFCLK+ REFCLK-
PWRDN/CAL
LOL
DOUT+ DOUT-
Recovered Data
Si5018
CLKOUT+ CLKOUT-
Recovered Clock
REXT
0.1 F
10 k (1%)
VDD
2200 pF
20 pF
Rev. 1.2
GND
VDD
9
Si5018
Functional Description
The Si5018 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLLTM technology to eliminate the noise entry points caused by external PLL loop filter components. no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5018 uses the reference clock to center the VCO output frequency at the OC-48/STM-16 data rate. The device will selfconfigure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.488 GHz and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies are given in Table 7.
DSPLLTM
The phase-locked loop structure (shown in "Typical Application Schematic" on page 9) utilizes Silicon Laboratories' DSPLLTM technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain.
Table 7. Typical REFCLK Frequencies
OC-48/ STM-16 (2.488 GHz) 19.44 MHz 77.76 MHz 155.52 MHz OC-48/STM-16 w/ 15/14 FEC (2.666 GHz) 20.83 MHz 83.31 MHz 166.63 MHz Ratio of VCO to REFCLK 128 32 16
PLL Self-Calibration
The Si5018 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on powerup. A self-calibration can be initiated by forcing a high-tolow transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 s before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories' "AN42: Controlling DSPLLTM Self-Calibration for the Si5020/5018/5010 CDR Devices and Si531x Clock Multiplier/Regenerator Devices."
Forward Error Correction (FEC)
The Si5018 supports FEC in SONET OC-48 (SDH STM-16) applications for data rates up to 2.7 Gbps. In FEC applications, the appropriate reference clock frequency is determined by dividing the input data rate by 16, 32, or 128. For example, if an FEC code is used that produces a 2.7 Gbps data rate, the required reference clock would be 168.75 MHz, 84.375 MHz, or 21.09 MHz.
Lock Detect
The Si5018 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out of lock, and the loss-oflock (LOL) pin is asserted high. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock may drift over a 600 ppm range relative to the applied reference clock, and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the
Reference Clock Detect
The Si5018 CDR requires an external reference clock applied to the REFCLK input for normal device operation. When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that
10
Rev. 1.2
Si5018
low noise and stability of the DSPLL, under the condition where data is removed from the inputs, there is the possibility that the PLL will not drift enough to render an out-of-lock condition. If REFCLK is removed, the LOL output alarm is always asserted when it has been determined that no activity exists on REFCLK, indicating the frequency lock status of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
Sinusoidal Input Jitter (UIPP)
20 dB/Decade Slope
15 1.5 0.15 f0 f1 f2
Frequency
PLL Performance
The PLL implementation used in the Si5018 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
f3
ft
SONET Data Rate OC- 48
F0 (Hz) 10
F1 (Hz) 600
F2 (Hz) 6000
F3 (kHz) 100
Ft (kHz) 1000
The Si5018's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 4. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device.
Jitter Transfer
Figure 4. Jitter Tolerance Specification
Jitter Trans f er
The Si5018 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 5). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 4.
Jitter Generation
0.1 dB A c c eptable Range
20 dB / Dec ade Slope
The Si5018 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5018 generates less than 3.0 mUIrms of jitter when presented with jitter free input data.
Fc Frequenc y
S ONET Da ta Ra te OC- 48
Fc (kHz) 2000
Figure 5. Jitter Transfer Specification
Powerdown
The Si5018 provides a powerdown pin, PWRDN/CAL, that disables the output drivers (DOUT, CLKOUT). When the PWRDN/CAL pin is driven high, the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. When PWRDN/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream.
Rev. 1.2
11
Si5018
Device Grounding
The Si5018 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location.
Differential Input Circuitry
The Si5018 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
Bias Generation Circuitry
The Si5018 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
Dif f erential Driv er
Si5018 V DD
2.5 k 0.1 F Z o = 50 D IN +, R F C LK +
10 k 0.1 F Z o = 50 D IN -, R F C LK -
2.5 k
102
10 k
GND
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Si5018 Clock source
0.1 F Zo = 50 REFCLK + 10 k 100 REFCLK - 10 k 0.1 F 2.5 k
VDD
2.5 k
102
GND
Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled)
12
Rev. 1.2
Si5018
Si5018 Clock source
0.1 F Zo = 50 DIN + 10 k 100 DIN - 10 k 0.1 F 2.5 k
VDD
2.5 k
102
GND
Figure 8. Single-Ended Input Termination for DIN (AC Coupled)
Rev. 1.2
13
Si5018
Differential Output Circuitry
The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6.
Si5018 V DD
100
V DD
50
DOUT +, CLKOUT +
0.1 F
Z o = 50
DOUT -, CLKOUT -
0.1 F
Z o = 50
100
V DD
50
V DD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
14
Rev. 1.2
Si5018
Pin Descriptions: Si5018
CLKOUT+ CLKOUT-
GND
GND
20 19 18 17 16 REXT VDD GND REFCLK+ REFCLK- 1 2 3 4 5 6
LOL
GND
15
PWRDN/CAL VDD DOUT+ DOUT- VDD
GND Pad Connection
14 13 12 11
7
VDD
8
GND
9
DIN+
10
DIN-
Figure 10. Si5018 Pin Configuration Table 8. Si5018 Pin Descriptions
Pin # Pin Name I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor.
1
REXT
4 5
REFCLK+ REFCLK-
I
See Table 2
Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. Loss-of-Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 7. Differential Data Input. Clock and data are recovered from the differential signal present on these pins. Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT.
6
LOL
O
LVTTL
9 10 12 13
DIN+ DIN- DOUT- DOUT+
I
See Table 2
O
CML
Rev. 1.2
15
Si5018
Table 8. Si5018 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Powerdown. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration" on page 10.)
Note: This input has a weak internal pulldown.
15
PWRDN/CAL
I
LVTTL
16 17
CLKOUT- CLKOUT+
O
CML
Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK. Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground.
2, 7, 11, 14 3, 8, 18, 19, 20, and GND Pad
VDD GND
2.5 V GND
16
Rev. 1.2
Si5018
Ordering Guide
Part Number Package Temperature
SI5018-BM
20-pin MLP
-40 to 85 C
Top Mark
Silicon Labs Part Number
Die Revision (R)
Part Designator (Z)
SI5018-BM
B
C
Rev. 1.2
17
Si5018
Package Outline: SI5018-BM
Figure 11 illustrates the package details for the SI5018-BM. Table 9 lists the values for the dimensions shown in the illustration.
D D1 PIN1 ID 0.50 DIA. 20
A A1 A2 A3 b b 1 2 3 e e D2 L 20
1 2 3
E1
E
E2
Top View
Side View
Bottom View
Figure 11. 20-pin Micro Leadframe Package (MLP) Table 9. Package Dimensions
Symbol Min Millimeters Nom Max Symbol Min Millimeters Nom Max
A A1 A2 A3 b D, E
-- 0.00 -- 0.18
0.85 0.01 0.65 0.20 REF. 0.23 4.00 BSC
0.90 0.05 0.70 0.30
D1, E1 D2, E2 e L -- 0.50 1.95
3.75 BSC 2.10 0.50 BSC -- 0.60 12 0.75 2.25
Notes: 1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 2. Package warpage MAX 0.05 mm. 3. "b" applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP. 4. The package weight is approximately 42 mg. 5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28 minimum/54 typical. 6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
18
Rev. 1.2
Si5018
4x4 mm 20L MLP Recommended PCB Layout
See Note 8 Gnd Pin
See Note 9
Gnd Pin
Symbol
Parameter Min
Gnd Pin
Dimensions Nom 2.25 2.08 0.50 BSC 2.46 0.12 REF 0.25 0.94 REF 4.28 Max 2.28 2.13 -- 2.48 -- 0.28 -- 4.31
A D e G R X Y Z
Pad Row/Column Width/Length Thermal Pad Width/Height Pad Pitch Pad Row/Column Separation Pad Radius Pad Width Pad Length Pad Row/Column Extents
2.23 2.03 -- 2.43 -- 0.23 -- 4.26
Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad. 3. The center thermal pad is to be Solder Mask Defined (SMD). 4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent solder from flowing into the via hole. 5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a 0.65 mm pitch, should be used for the center thermal pad. 6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate paste release. 7. A "No-Clean", Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended. 8. Do not place any signal or power plane vias in these "keep out" regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
Rev. 1.2
19
Si5018
Document Change List
Revision 1.0 to Revision 1.1
! !
Added "Top Mark" on page 17. Updated "Package Outline: SI5018-BM" on page 18. ! Added "4x4 mm 20L MLP Recommended PCB Layout" on page 19.
Revision 1.1 to Revision 1.2
!
Made minor note corrections to "4x4 mm 20L MLP Recommended PCB Layout" on page 19.
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Rev. 1.2
Si5018
Notes:
Rev. 1.2
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Si5018
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, DSPLL, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 1.2

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